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任意分频代码(VHDL)
- 任意分频代码(VHDL)
FPQ.rar
- 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频,Divider vhdl descr iption of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
FPQ.rar
- VHDL实现分频器 有仿真图 有实验报告,VHDL simulation of the realization of crossovers have the report there were experimental
半整数分频器的实现（verilog）
- 半整数分频器的实现（verilog），本文以6.5分频为例！很实用的！,fen pin qi
zz.rar
- 键控加/减计数器,将20MHz系统时钟经分频器后可得到5M、1M、100K、10K、5K、1K、10Hz、1Hz ,Keying increase/decrease counter to 20MHz system clock by the divider available after 5M, 1M, 100K, 10K, 5K, 1K, 10Hz, 1Hz
music
- 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
VHDL
- 一个实现整数分频的VHDL代码，只要把n设置成你所需要的分频的数值就行-A realization of an integer divider of the VHDL code, as long as the n set you need the sub-frequency values on the line
divider
- 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value o
clock_divider
- 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed descr iption of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL
fpga1223344
- 基于FPGA的分频器,可以根据更改参数,实现不同倍数的分频.-FPGA-based prescaler, can change the parameters, different multiples of the sub-frequency.
vhdl-devider
- 基于vhdl的分频器设计，分频器在数字系统设计中应用频繁-VHDL-based design of the divider, divider in the digital system design applications frequently
time_div
- IP 分频器 可以通过输入参数而自动调整分频数-IP divider input parameters can be automatically adjusted at the frequency
ab
- 能实现2分之1分频器，4分之1分频器，8分之1分频器等功能-To achieve half divider, prescaler fourth, eighth divider functions
ghzfchsa
- 数控分频器，可实现50m以内任意整数分频-NC divider can be realized within 50m of arbitrary integer frequency
VHDL
- 用VHDL写的代码，实现任意整数分频，自己只要修改分频参数即可。希望对大家有用-Written in VHDL code used to achieve arbitrary integer frequency, their frequency as long as the modified parameter. We hope to be useful
FPQ
- 基于FPGA的数控分频器，可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.
fenpinji
- 设计了一种分频器，能够将所给的频率分成较小的频率。可以适当修改其中的参数，使频率达到设计者要求-The design of a prescaler, which can be divided into smaller frequency to frequency. Appropriate changes to the parameters, so that the frequency of the designer to achieve the requirements
vhdl分频器设计
- vhdl分频器设计，用quartus软件偏写，可进行时钟的分频。(Design of VHDL frequency divider)
分频显示
- VHDL实验中，实现分频与数码管显示。掌握BCD-七段显示译码器的功能和设计方法； 掌握用硬件描述语言的方法设计组合逻辑电路——BCD-七段显示译码器。(In the VHDL experiment, frequency division and digital tube display are realized.)